/*
 * pc.v
 *
 * Copyright 2024 dh33ex <dh33ex@riseup.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA or visit <http://www.gnu.org/licenses/>.
 *
 *
 */

module pc(
    input                i_clk,
    input                i_rst,
    input       [31:0]   i_reg3,
    input       [23:0]   i_offset,
    input       [1:0]    i_PC_sel,

    output reg  [31:0]   o_PC
);

    always @(posedge i_clk) begin
        if (i_rst) begin
            o_PC <= 32'd0;
        end else begin
            case(i_PC_sel)
                2'b00: o_PC <= i_reg3;
                2'b01: o_PC <= o_PC + 4 + {{8{i_offset[23]}}, i_offset};
                2'b10: o_PC <= o_PC + 4;
                default: o_PC <= 32'hxxxxxxxx;
            endcase
        end
    end

endmodule
